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1 narrow vdc regulator/charger with smbus interface and internal switching fets isl9519c the isl9519c is a highly integrated narrow vdc system voltage regulator and battery charger controller. operating parameters are programmable over the syst em management bus (smbus). the isl9519c is designed for applications where the system power source is either the batt ery pack or the output of the regulator/charger. this makes the max voltage to the system equal to the max battery voltage instead of the max adapter voltage. the isl9519c also includes a patented system to control trickle charging deeply discharged batteries while maintaining system voltage at a user defined minimum. high efficiency is achieved with a dc/dc synchronous-rectifier buck converter, equipped with diode emulation and variable switching frequency for enhanced light load efficiency and ac-adapter boosting prevention. the isl9519c can charge one, two or three series connected lithium-ion cells, at up to 8a charge current. default settings for 1-, 2- or 3-cell operation at power-up are selected by an external pin. integrated mosfets, drivers and bootstrap diode result in fewer components and smaller implementation area. low offset current-sense amplifiers provide high accuracy. the isl9519c provides an open drain digital output that indicates the presence of the ac-adapter. the isl9519c also provides an analog output that indicates the adapter current. applications ? notebook computers ? tablet pcs ? portable equipment with rechargeable batteries features ? 0.5% system voltage accuracy (-10c to +100c) ? 3% accurate input current limit ? 3% accurate battery charge current limit ? variable switching frequency at light load conditions for higher efficiency ? fixed frequency operation at higher loads - fixed frequency mode can be forced by an external pin ? trickle charge system for deeply discharged batteries -automatic trickle ch arge current (256ma) - holds minimum voltage to system ? smbus 2-wire serial interface ? default system voltage values for 1-cell, 2-cell or 3-cell operation selected by an external pin ?adapter in-rush fet control ? adapter isolation fet control ? battery short circuit protection ? fast system-load transient response ? monitor outputs - adapter current (2.5% accuracy) - ac-adapter present indicator ? 11-bit max system voltage setting ? 7-bit min system voltage setting ? 6-bit charge current setting - over 8a battery charger current ? 6-bit adapter current setting - over 8a adapter current ? +4.5v to +22v adapter voltage range ? pb-free (rohs compliant) figure 1. efficiency figure 2. max load current vs ambient temperature with 1m/s forced air cooling 70 75 80 85 90 95 100 012345678 system load (a) efficiency (%) 3 cell (12.6v) 2 cell (8.4v) 2 cell (6v) 1 cell (4.2v) 1 cell (3v) 0 1 2 3 4 5 6 7 8 25 45 65 85 105 125 max ambient temperature (c) max output current (a) 3 cell (12.6v) 2 cell (8.4v) 2 cell (6v) 1 cell (4.2v) 1 cell (3v) june 30, 2011 fn7823.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 |copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl9519c 2 fn7823.0 june 30, 2011 pin configuration isl9519c (50 ld tqfn) top view table 1. isl9519 family part number logic levels pin 9 function default adapter current limit internal switching fets isl9519 3.3v or 5v pull-up amon (adapter current monitor) 3.584a no isl9519c 3.3v or 5v pull-up amon (adapter current monitor) 3.584a yes isl9519r 3.3v or 5v pull-up amon (adapter current monitor) 0.128a no isl9519q 1.8v or 2.5v pull-up ccmon (charge current monitor) 3.584a no 1 2 3 4 5 6 7 50 49 48 47 46 45 44 17 18 19 20 21 23 acok bgate cson csop phase phase nc vin vin vfb rst# sda vsmb amon phase vcomp cell scl agnd agnd 43 24 vin icomp 9 10 11 12 vddp pgnd vdd agnd phase 41 40 39 38 37 36 35 34 33 32 31 30 agate adet csin sgate dcin boot csip ugate vin ugate agnd vin vin phase 51 53 42 25 vin vfsw 22 phase 52 29 vin 28 vin 27 vin 26 vin 13 pgnd 14 pgnd 15 pgnd 16 pgnd 8 agnd functional pin descriptions pin number symbol description 1 vsmb smbus interface supply voltage input. bypass with a 0.1f capacitor to agnd. 2 rst# logic input sets all smbus regi sters to default values when low. 3 acok ac detect output. this open drain output is high impedance when adet is greater than 3.2v. the acok output remains low when the isl9519c is powered down. connect a 10k pull-up resistor from acok to vsmb. 5 bgate gate drive for the battery connection pfet. this pin can go high to disconnect the battery, low to connect the battery or operate in a linear mode to regulate mini mum system voltage during trickle charge. it is also the compensation point for the min system voltage regulation loop.
isl9519c 3 fn7823.0 june 30, 2011 6 cson charge current-sense negative input and system voltage feedback. 7 csop charge current-sense positive input. 4, 8, 34, 45, 51 agnd ground connection fo r low power analog and digital circuits. 9 vdd linear regulator output. vdd is the output of the 5.1v linear regulator supplied from dcin. vdd supplies regulated power input for internal analog circuits. connect a 4.7 ? resistor from vdd to vddp and a 1f ceramic capacitor from vdd to agnd. 10 vddp vddp directly supplies the lgate driver and the bo ot strap diode. bypass with a 1f ceramic capacitor from vddp to pgnd. 11, 17, 18, 19, 20, 52 phase switching power output. connect to the inductor. 12, 13, 14, 15, 16 pgnd power ground. connect pgnd to the system or power ground. 21 nc nc. 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 53 vin high-side power mosfet drain. connect to the powe r input and decouple with low esr capacitors to pgnd. 32, 33 ugate high-side power mosfet driver output and the gate of the high side fet. connect a 4700pf cap from ugate to phase. 35 boot high-side power mosfet driver power-supply conn ection. connect a 0.1f capacitor from boot to phase. 36 sgate system gate pfet driver. controls the adapter connec tion fet that blocks current flow from the battery to the adapter connector. 37 csin adapter current-sense negative input. 38 csip adapter current-sense positive input. 39 agate adapter gate (in-rush) fet control (open drain output). 40 dcin charger bias supply input. bypass dcin with a 0.1f capacitor to agnd. 41 adet ac-adapter detection input. connect to a resistor divider from the ac-adapter output. 42 vfsw logic input enables variable frequency switching at light loads. 43 icomp output of the current control error amplifier. 44 cell logic level input selects 1-cell, 2-cell or 3-cell default maxsystemvoltage and minsystemvoltage register values. floating the cell pin selects 1-cell. pulling cell to vsmb selects 3-cell and pulling cell low selects 2-cell defaults. the cell pin is read only at vsmb por or rst#. 46 vcomp output of the voltage loop error amplifier. 47 vfb negative input to the min system voltage and max system voltage control error amplifier. 48 amon input current monitor output. amon voltage equals 20 x (v csip - v csin ). 49 sda smbus data i/o. open-drain output. connect an external pull-up resistor according to smbus specifications. 50 scl smbus clock input. connect an external pull -up resistor according to smbus specifications. 51 agnd connect the backside paddle to agnd and pgnd (pins 8 and 12) and the system ground plane. functional pin descriptions (continued) pin number symbol description ordering information part number (notes 1, 2) part marking temp range (c) package (pb-free) pkg. dwg. # ISL9519CHRZ isl 9519chrz -10 to +100 50 ld 5x7 qfn l50.5x7b notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb- free products are msl classified at pb-free peak reflow temperat ures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl9519c . for more information on msl please see techbrief tb363 .
isl9519c 4 fn7823.0 june 30, 2011 table of contents functional pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . 8 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 smb timing specification . . . . . . . . . . . . . . . . . . . . . . . . . 10 typical operating performance . . . . . . . . . . . . . . . . . . . . . . . . 11 theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 pwm control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ac-adapter detection. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 vdd regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 vsmb supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 current measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 14 sgate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 agate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 bgate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 trickle charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 short circuit protection and 0v battery charging . . . 14 over-temperature protection . . . . . . . . . . . . . . . . . . . . 14 the system management bus . . . . . . . . . . . . . . . . . . . 14 general smbus architecture . . . . . . . . . . . . . . . . . . . . . 15 data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . 15 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 smbus transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 byte format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 isl9519c and smbus . . . . . . . . . . . . . . . . . . . . . . . . . . 16 smbus registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 setting max system voltage . . . . . . . . . . . . . . . . . . . . 16 smart battery registers . . . . . . . . . . . . . . . . . . . . . . . . 17 max accepted max system voltage command . . . . . . . . . . 17 setting minimum system voltage . . . . . . . . . . . . . . . . . . . . . 17 bgate and 1 cell operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 setting charge current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 setting input current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 charger timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 isl9519c data byte order . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 writing to the internal registers . . . . . . . . . . . . . . . . . . . . . . . 20 reading from the internal registers . . . . . . . . . . . . . . . . . . . 20 application information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 output capacitor selection. . . . . . . . . . . . . . . . . . . . . . 21 snubber design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . .21 loop compensation design . . . . . . . . . . . . . . . . . . . . .21 transconductance amplifiers gm1, gm2, gm3 and gm4 . . . . . . . . . . . . . . . . . . . . .21 pwm gain fm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 output lc filter transfer functions. . . . . . . . . . . . . . . 22 max system voltage control loop . . . . . . . . . . . . . . . .22 compensation break frequency equations . . . . . . . . 22 charge current control loop . . . . . . . . . . . . . . . . . . . . 23 adapter current limit control loop . . . . . . . . . . . . . . 24 min system voltage control loop . . . . . . . . . . . . . . . . .24 guidelines for layout and component placement . . . . . . . 24 vin (input power) capacitors . . . . . . . . . . . . . . . . . . . . 25 vddp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 ugate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 copper size for the phase node . . . . . . . . . . . . . . . . . .25 boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 csop, cson, csip and csin . . . . . . . . . . . . . . . . . . . . .26 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 package outline drawing. . . . . . . . . . . . . . . . . . . . . . . . . . 28
isl9519c 5 fn7823.0 june 30, 2011 figure 3. functional block diagram smbus vsmb dc/dc converter sda csop phase ugate boot pgnd vddp scl cson csip csin icomp vdd 6 6 11 linear regulator dcin sgate adet acok vref amon en disconnect adapter ac_ok trickle 7 agate disconnect adapter charge current adapter current maxsystemvoltage minsystemvoltage cc dac ac dac ac dac cc dac maxsvdac 20x + - + - gm2 vmin imin 20x + - + - minsvdac cson 100k 500k bgate + - gm1 + - trickle trickle ac_ok isl9519c vcomp vfb agnd minsvdac maxsvdac vfsw vfsw + - gm4 + - gm3 low power cell 0.1v + - low freq at light load sgate on sgate on vin vfsw rst#
isl9519c 6 fn7823.0 june 30, 2011 figure 4. typical application circuit ac-adapter to battery to system rs1 rs2 agnd pgnd agnd phase boot ugate csin csip csop cson adet scl dcin sda vsmb amon vddp acok agnd agate bgate icomp vcomp vdd vfb host pgnd pgnd agnd cell agnd agnd isl9519c vin vfsw rst# sgate pgnd
isl9519c 7 fn7823.0 june 30, 2011 figure 5. typical 5v input application circuit ac-adapter to battery to system rs1 rs2 agnd pgnd agnd phase boot ugate csin csip csop cson adet scl dcin sda vsmb amon vddp acok agnd agate bgate icomp vcomp vdd vfb host pgnd pgnd agnd cell agnd agnd isl9519c vin input overvoltage protection 5.1v vfsw rst# pgnd
isl9519c 8 fn7823.0 june 30, 2011 absolute maximum rating s thermal information dcin, csip, cson, agate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +28v csip-csin, csop-cson, pgnd-agnd-. . . . . . . . . . . . . . . . . . . 0.3v to +0.3v boot voltage (v boot-gnd ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 33v boot to phase voltage (v boot-phase ). . . . . . . . . . . . . . . . . . . . -0.3v to 7v phase voltage (note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . pgnd - 0.3v to 30v ugate voltage. . . . . . . . . . . . . . . . . . . . . . . . . . v phase - 0.3v (dc) to v boot amon, icomp, vcomp, vfb . . . . . . . . . . . . . . . . . . . . . .-0.3v to vdd + 0.3v vsmb, scl, sda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v adet, acok, cell, vfsw, rst# . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v vddp, vdd to agnd, vddp to pgnd . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v bgate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . agnd - 0.3v to cson + 0.3v cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to vsmb + 0.3v thermal resistance (typical) ja (c/w) jc (c/w) 50 ld tqfn package (notes 5, 6) 32 2 operating junction temperature range . . . . . . . . . . . . . .-10c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp operating conditions temperature range (see figure 8). . . . . . . . . . . . . . . . . . .-10c to +100c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. the phase voltage is capable of withstan ding -7v when the boot pin is at gnd. 5. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379. 6. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications dcin = csip = csin = 19v, csop = cson = 12v, vddp = 5v, vsmb = 3.42v, boot-phase = 5v, agnd = pgnd = 0v, cvdd = 1f, t a = -10c to +100c. boldface limits apply over the operating temperature range, -10c to +100c. parameter conditions min (note 8) typ max (note 8) units system voltage regulation maximum system voltage accuracy maxsystemvoltage = 0x3130 12.529 12.592 12.655 v -0.5 0.5 % maxsystemvoltage = 0x20d0 8.358 8.4 8.442 v -0.5 0.5 % maxsystemvoltage = 0x1060 4.171 4.192 4.213 v -0.5 0.5 % minimum system voltage accuracy minsystemvoltage = 0x2400 8.940 9.216 9.492 v -3 3 % minsystemvoltage = 0x1800 5.898 6.144 6.390 v -4 4 % minsystemvoltage = 0x0c00 2.888 3.072 3.256 v 66 % charge current regulation charge current and accuracy rs2 = 10m ? (see figure 4) chargingcurrent = 0x1f80 7.822 8.064 8.306 a -3 3 % rs2 = 10m ? (see figure 4) chargingcurrent = 0x1000 3.973 4.096 4.219 a -3 3 % rs2 = 10m ? (see figure 4) chargingcurrent = 0x0100 166 256 346 ma trickle charge current rs2 = 10m ? (see figure 4) cson-bgate < 4.3v or bgate < 1v 166 256 346 ma trickle charge threshold cson-bgate 4.0 4.7 5.5 v battery quiescent current i csop + i cson + i phase + i csip + i csin + i agate v phase = v boot = v cson = v csop = v csin = v csip = v agate = 12.6v, v dcin = vdd = vddp = 0v 14 25 a
isl9519c 9 fn7823.0 june 30, 2011 input current regulation input current accuracy rs1 = 20m ? (see figure 4) adapter current = 512ma -7 7 % rs1 = 20m ? (see figure 4) adapter current = 4096ma or 8064ma -3 3 % csip/csin input voltage range 526 v amon accuracy ideal amon = 20*(csip-csin) v csip-csin = 161.28mv, amon load < 1a -2.5 2.5 % v csip-csin = 81.92mv amon load < 1a -4 4 % v csip-csin = 10.24mv, amon load < 1a -20 20 % v csip-csin = 5.12mv, amon load < 1a -40 40 % amon min output voltage v csip-csin = 0.0v, amon load < 1a 30 80 mv amon max source current v csip-csin = 161.28mv, v amon = 0v 25 40 60 a amon max sink current v csip-csin = 0.0v, v amon = 2v 25 40 60 a supply and linear regulator dcin, input voltage range 626 v dcin quiescent current v adapter = 5.5v to 26v, v battery 4v to 16v 2 5 ma vdd output voltage 6.0v < v dcin < 26v, no load 4.975 5.1 5.23 v vdd load regulation 0 < i vddp < 30ma (see note 6) 35 mv vdd uvlo rising 3.93 4.0 4.12 v vdd uvlo hysteresis 170 235 325 mv vsmb range 2.7 5.5 v vsmb uvlo rising 2.5 2.75 2.95 v vsmb uvlo hysteresis 75 125 175 mv vsmb quiescent current vsmb = scl = sda = 3.42v 30 50 a vsmb quiescent current vsmb = scl = sda = 3.42v, low power bit = 1 14 25 a adet adet rising threshold 3.15 3.2 3.25 v adet threshold hysteresis 35 60 90 mv adet input leakage current 1 a acok sink current v acok = 0.4v, adet = 2.7v 2 8ma leakage current v acok = 5.5v, adet = 3.7v 1 a agate sink current v adet > 3.5v, agate = 0.4v 1 2.3 ma leakage current v adet = 0v, agate = 26v 1 a sgate csip-csin threshold for sgate going high 6.6 9 mv csip-csin threshold hysteresis 1.5 3.3 mv sink current csip-csin > 10mv, agate = 0.4v 1 2.3 ma leakage current csip-csin = 0v, agate = 26v 1 a electrical specifications dcin = csip = csin = 19v, csop = cson = 12v, vddp = 5v, vsmb = 3.42v, boot-phase = 5v, agnd = pgnd = 0v, cvdd = 1f, t a = -10c to +100c. boldface limits apply over the operating temperature range, -10c to +100c. (continued) parameter conditions min (note 8) typ max (note 8) units
isl9519c 10 fn7823.0 june 30, 2011 vfsw vfsw input low voltage 0.8 v vfsw input high voltage 2 v vfsw input leakage current 1 a rst# input low voltage vsmb = 2.7v to 5.5v 0.8 v input high voltage vsmb = 2.7v to 5.5v 2 v input leakage current vsmb = 2.7v to 5.5v 1 a battery cell selector cell input voltage for 3-cell select vsmb -0.4 v cell input voltage for 1-cell select 0.85 vsmb -1.2 v cell input voltage for 2-cell select 0.4 v cell input current lo cell = gnd, rst# = gnd -40 a cell input current hi ce ll = vsmb, rst# = gnd 40 a cell float voltage cell = open, rst# = gnd 1.23 v cell input current hi z cell = 0v or vsmb, rst# = vsmb 0.05 1 a switching regulator frequency 400khz register 0x3d = xx1x0x00b 330 400 440 khz max variable frequency register 0x3d = xx1x1x0xb, ccm load 330 400 440 khz min variable frequency 1 register 0x3d = xx1x1x0xb, no load 140 khz min variable frequency 2 register 0x3d = xx1x1x1xb, no load 80 khz error amplifiers gm2 amplifier transconductance transconductance from vfb to vcomp 200 250 300 a/v gm1 amplifier transconductance transconductance from (csop-cson) to icomp 40 50 60 a/v gm3 amplifier transconductance transconductance from (csip-csin) to icomp 40 50 60 a/v gm4 amplifier transconductance transconductance from vfb to bgate 50 100 150 a/v gm1/gm3 saturation current 15 21 25 a gm2 saturation current 10 17 25 a icomp, vcomp clamp voltage max voltage between v vcomp and v icomp 200 300 400 mv logic levels sda/scl input low voltage vsmb = 2.7v to 5.5v 0.8 v sda/scl input high voltage vsmb = 2.7v to 5.5v 2 v sda/scl input bias current vsmb = 2.7v to 5.5v 1 a sda, output sink current v sda = 0.4v 4 12 ma electrical specifications dcin = csip = csin = 19v, csop = cson = 12v, vddp = 5v, vsmb = 3.42v, boot-phase = 5v, agnd = pgnd = 0v, cvdd = 1f, t a = -10c to +100c. boldface limits apply over the operating temperature range, -10c to +100c. (continued) parameter conditions min (note 8) typ max (note 8) units smb timing specification vsmb = 2.7v to 5.5v. parameters symbol conditions min (note 8) typ max (note 8) units smbus frequency fsmb 10 100 khz bus free time t buf 4.7 s
isl9519c 11 fn7823.0 june 30, 2011 start condition hold time from scl t hd:sta 4s start condition set-up time from scl t su:sta 4.7 s stop condition set-up time from scl t su:sto 4s sda hold time from scl t hd:dat 300 ns sda set-up time from scl t su:dat 250 ns scl low period t low 4.7 s scl high period t high 4s smbus inactivity time-out maximum charging period without a smbus write to maxsystemvoltage or chargecurrent register 120 180 250 s notes: 7. limits should be considered typical and are not production tested. 8. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. smb timing specification vsmb = 2.7v to 5.5v. (continued) parameters symbol conditions min (note 8) typ max (note 8) units typical operating performance dcin = 20v, 2s2p li-battery, t a = +25c, unless otherwise noted. figure 6. charge current and system voltage vs battery voltage 0 1 2 3 4 5 6 7 8 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 battery current (a) 4.5 9 volt (v) 01 2 3 4 5 67 8 battery voltage (v) smbus commands: max system voltage = 8.4v min system voltage = 5.376v charge current = 3.584a fully enhanced the bgate fet is in fast charge mode when battery voltage exceeds min system voltage system voltage = minsystem voltage in trickle charge mode v battery ramps up from zero to maxsystemvoltage bgate in thelinear mode for trickle charge charge current increases to fast charge trickle charge current 9
isl9519c 12 fn7823.0 june 30, 2011 figure 7. efficiency figure 8. max load current vs ambient temperature with 1m/s forced air cooling figure 9. load regulation figure 10. maxsystemvoltage command accuracy figure 11. charge current command accuracy figure 12. adapter current limit accuracy typical operating performance dcin = 20v, 2s2p li-battery, t a = +25c, unless otherwise noted. (continued) 70 75 80 85 90 95 100 012345678 system load (a) efficiency (%) 3 cell (12.6v) 2 cell (8.4v) 2 cell (6v) 1 cell (4.2v) 1 cell (3v) 0 1 2 3 4 5 6 7 8 25 45 65 85 105 125 max ambient temperature (c) max output current (a) 3 cell (12.6v) 2 cell (8.4v) 2 cell (6v) 1 cell (4.2v) 1 cell (3v) -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 10 12 load (a) maxsystemvoltage load regulation (%) 468 2 0 spec limit spec limit msv = 4.208v msv = 12.592v msv = 8.4v -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 246810121416 command (v) maxsystemvoltage accuracy (%) load = 10ma to 8ma spec limit spec limit -20 -15 -10 -5.0 0.0 5.0 10 15 20 charge current command (a) 1234 56789 0 accuracy (%) v bat = 11.6v spec limit spec limit v bat = 6v v bat = 3.2v -10 -8 -6 -4 -2 0 2 4 6 8 10 adapter current limit command (a) accuracy (%) 012 34 5 6 789 spec limit spec limit 3 cell 1 cell 2 cell
isl9519c 13 fn7823.0 june 30, 2011 theory of operation introduction a high efficiency synchronous buck converter is used to control the system voltage up to 16.368v and charging current up to 6a. the isl9519c also has input curre nt limiting up to 8.064a (or higher with lower values of sense resistor). the input current limit, charge current limit, minimum and maximum system voltage are set by internal registers written with smbus. the isl9519c ?typical application circuit? on page 6 is depicted in figure 4. the isl9519c charges the battery with constant charge current, set by the chargecurrent register, until the battery voltage rises to a voltage set by the maxsystemvoltage register. the charger will then operate at a co nstant voltage. the adapter current is monitored and if the adapter current rises to the limit set by the inputcurrent register, system voltage and battery charge current are reduced to limit adapter current. if battery voltage is below the min system voltage, the trickle charge system is activated. the isl9519c features two volt age regulation loops and two current regulation loops. the ma x system voltage loop controls the voltage at cson with a pr ecision voltage divider to the voltage error amplifier gm2. the min system voltage prevents the system voltage from dropping below a minimum value even if a deeply discharged battery is inserted that is below the minimum. the charge current regu lation loop limits the battery charging current delivered to the battery to ensure that it never exceeds the current set by the chargecurrent register. the input current regulation loop limits the current drawn from the ac-adapter to ensure that it never exceeds the limit set by the inputcurrent register to prevent adapter overload. figure 13. amon accuracy figure 14. light load, low frequency switching waveforms (lgate is internal) figure 15. switching waveforms in discontinuous conduction mode (lgate is internal) figure 16. switching waveforms in continuous conduction mode (lgate is internal) typical operating performance dcin = 20v, 2s2p li-battery, t a = +25c, unless otherwise noted. (continued) -10 -8 -6 -4 -2 0 2 4 6 8 10 adapter current 012 34567 89 accuracy (%) spec limit spec limit 3 cell 1 cell 2 cell phase ugate lgate inductor current inductor current lgate phase ugate phase p l a c e h o l d e r inductor current lgate ugate phase phase
isl9519c 14 fn7823.0 june 30, 2011 pwm control the isl9519c employs a variable frequency pulse width modulator (pwm) with feed-forward. the switching frequency is constant in continuous conduction mode (ccm) but is reduced in discontinuous mode (dcm). switching frequency can be fixed by setting bits in the control regi ster and/or pulling the vfsw pin low. ac-adapter detection ac-adapter voltage is connected through a resistor divider to adet to detect when ac power is available, as shown in figure 4. acok is an open-drain output and is active low when adet is less than v th,fall , and high z when adet is above v th,rise . the adet rising threshold is 3.2v (typ) with 57mv hysteresis. adet must be above the threshold to en able the output voltage. vdd regulator vdd provides a 5.1v supply vo ltage from the internal ldo regulator from dcin and can deliv er up to 30ma of continuous current. vdd also supplies power to vddp through a low pass filter, as shown in the ?typical application circuit? on page 6 in figure 4. the mosfet drivers are powered by vddp. bypass vddp and vdd with a 1f capacitor. vsmb supply the vsmb input provides power to the smbus interface. connect an external supply to vsmb to keep the smbus interface active while the supply to dcin is remo ved. when vsmb is biased, the internal registers are maintained. bypass vsmb to agnd with a 0.1f or greater ceramic capacitor. current measurement amon is an output voltage that is proportional to the adapter current being sensed across csip and csin. the output voltage range is 0.1v to 3.2v. the voltage of amon is given by equation 1: where i input is the dc current drawn from the ac-adapter. a capacitor is required at the amon output to stabilize the amon amplifier and to minimize switching noise. sgate function sgate is the system isolation fet. the sgate pin pulls low to turn an external pfet on when current flowing from the adapter to the system exceeds a threshold (see ?electrical specifications? table on page 9). sgate is high (open drain) when the adapter current drops below the threshold. when the sgate fet is off, its body diode blocks current flow from the system to the adapter connector. agate function agate controls the adapter isolation fet. the agate pin pulls low to turn an external pfet on when adapter voltage is above a threshold set by resistor divider to adet. agate is high (open drain) when adet is less than 3.2v. when the agate fet is off, its body diode blocks current flow from the adapter to the system. a capacitor between the gate and source of th e agate fet can slow the turn-on of the fet and reduce in-rush current. the agate fet can be forced off by the islolate_adapter bit in the control register. bgate function the bgate pin drives the gate of an external pfet to control the minimum system voltage. if a battery is connected that is discharged below the value set in the minsystemvoltage register, bgate controls the system voltage at the value set in the minsystemvoltage register. trickle charging if a battery that is discharged below the value set in the minsystemvoltage register is conn ected to the system, the trickle charge system is activated. in trickle charge mode, the charge current is reduced to 256ma. the value in the chargecurrent register is not changed. the bgate fet is controlled in a linear mode to regulate the system voltage at min system voltage and to drop voltage between the min system voltage and the battery. this state is communicated to the host system by the trickle bit in the control register. when the battery is charged to the min system voltage, the bgate fet becomes fully enhanced and bg ate is pulled more than 4.5v below the system voltage or to grou nd in a 1-cell application. this changes the charge mode from trickle to fast charge. the charge current is increased to the value in the chargecurrent register. the trickle bit in the control register is set to 0. short circuit protection and 0v battery charging if a battery is connected that is completely discharged or a short circuit, the trickle charge system is activated. the charge current is reduced to 256ma and bgate controls the bgate fet to maintain system voltage at the value in the minsystemvoltage register. over-temperature protection if the die temperature exceeds +150c, it turns both of the synchronous buck fets off. the system bus and the battery charging are disabled. once the die temp drops below +125c, system bus regulation and battery charging will start-up again. the system management bus the system management bus (smbus) is a 2-wire bus that supports bidirectional communicat ions. the protocol is described briefly here. more detail is available from http://www.smbus.org . amon 20 i input r s1 ?? = (eq. 1)
isl9519c 15 fn7823.0 june 30, 2011 general smbus architecture data validity the data on the sda line must be stable during the high period of the scl, unless generating a start or stop condition. the high or low state of the data line can only change when the clock signal on the scl line is low. refer to figure 18. start and stop conditions as shown in figure 19, start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high transition on the sda line while scl is high. a stop condition must be sent before each start condition. acknowledge each address and data transmission uses 9-clock pulses. the ninth pulse is the acknowledge bit (ack). after the start condition, the master sends 7 slave address bits and a r/w bit during the next 8-clock pulses. during the ni nth clock pulse, the device that recognizes its own address holds the data line low to acknowledge (as shown in figure 20). the acknowledge bit is also used by both the master and the slave to acknowledge receipt of register addresses and data. smbus transactions all transactions start with a control byte sent from the smbus master device. the control byte begins with a start condition, followed by 7-bits of slave a ddress (0001001 for the isl9519c) followed by the r/w bit. the r/w bit is 0 for a write or 1 for a read. if any slave devices on the smbus bu s recognize their address, they will acknowledge by pulling the serial data (sda) line low for the last clock cycle in the control byte. if no slaves exist at that address or are not ready to communicate, the data line will be 1, indicating a not acknowledge condition. once the control byte is sent, and the isl9519c acknowledges it, the 2nd byte sent by the master must be a register address byte such as 0x14 for the chargecurrent register. the register address byte tells the isl9519c which register the master will write or read. see table 2 for details of the registers. once the isl9519c receives a register address byte it responds with an acknowledge. vdd smb sda scl scl smbus master cpu sda to other slave devices state machine registers memory etc output input scl control sda control output input smbus slave scl sda smbus slave state machine registers memory etc input output input output control control control control input output input output figure 17. sda scl data line stable data valid change of data allowed figure 18. data validity sda scl start condition figure 19. start and stop waveforms stop condition sp sda scl figure 20. acknowledge on the smbus 1 2 8 9 acknowledge msb from slave start
isl9519c 16 fn7823.0 june 30, 2011 . byte format every byte put on the sda line must be 8-bits long and must be followed by an acknowledge bit. data is transferred with the most significant bit first (msb) an d the least significant bit last (lsb). the lo byte data is transferred before the hi byte data. isl9519c and smbus the isl9519c receives control inputs from the smbus interface. the serial interface complies with th e smbus protocols as documented in the isl9519c system management bus specification v1.1, which can be downloaded from http://www.smbus.org . the isl9519c uses the smbus read-word and write-word protocols (see figure 21) to communicate with the host system and a smart battery. the isl9519c is an smbus slave device and does not initiate communication on the bus. it responds to the 7-bit address 0b0001001_ (0x12). read address = 0b00010011 and write address = 0b00010010. in addition, the isl9519c has two identification (id) registers: a 16-bit device id register (0xff) and a 16-bit manufacturer id register (0xfe). the data (sda) and clock (scl) pi ns have schmitt-trigger inputs that can accommodate slow edges. choose pull-up resistors for sda and scl to achieve rise times according to the smbus specifications. the isl9519c is controlled by the data written to the registers described in table 2. smbus registers the isl9519c supports 7 internal re gisters (described in table 2) that use either write-word or read-word protocols (see figure 21). manufacturerid and deviceid are ?read only? registers and can be used to identify the isl9519c. on the isl9519c, manufacturerid always returns 0x0049 (ascii code for ?i? for intersil) and deviceid always returns 0x0003. setting max system voltage max system voltage is set by writing a valid 16-bit number to the 16-bit maxsystemvoltage register. the isl9519c ignores the first 4 lsbs and uses the next 11 bits to set the voltage dac. the max system voltage range of the isl9519c is limited by the number of cells selected at the cell pin. the maximum accepted commands for 1, 2, and 3 cells are listed in table 4. numbers requesting max system voltage greater than the value in table 4 are ignored. the smbus communication is not acknowledged (nak) and the maxsystemvoltage register is unchanged. the minimum command is 1.024v. all numbers requesting max system voltage below 1.024v result in a voltage set point of zero, which turns off the regulator. the trickle charge system is activated when the bgate fet is in its active region. fast charging is active when the bgate fet is fully enhanced (cson-bgate > 4.5v or bgate < 0.8v). figure 21. smbus/isl9519c read and write protocol a s a n p slave addr + w register addr hi byte data lo byte data a a a s a p slave addr + w register addr hi byte data lo byte data a a n s a slave addr + r p acknowledge no acknowledge s start p stop driven by the master driven by isl9519c write to a register read from a register table 2. isl9519c register summary register address register name read/write description isl9519c (1-cell) por state isl9519c (2-cell) por state isl9519c (3-cell) por state 0x14 chargecurrent read or write 6-bit charge current setting 0x0000 = 0a 0x0000 = 0a 0x0000 = 0a 0x15 maxsystemvoltage read or write 11-bit maxsystemvoltage setting 0x1000 = 4.096v 0x2000 = 8.192v 0x3000 = 12.288v 0x3d control read or write 8-bit control bit register 0x0000 0x0000 0x0000 0x3e minsystemvoltage read or write 7-bit minsystemvoltage setting 0x0c00 = 3.072v 0x1800 = 6.144v 0x2400 = 9.216v 0x3f inputcurrent read or write 6-bit input current setting 0x0e00 = 3.584a 0x0e00 = 3.584a 0x0e00 = 3.584a 0xfe manufacturerid read only manufacturer id 0x0049 0x0049 0x0049 0xff deviceid read only device id 0x0003 0x0003 0x0003
isl9519c 17 fn7823.0 june 30, 2011 upon initial power-up of the vsmb supply, the maxsystemvoltage register is reset to the por value in table 3. use the write-word protocol (figure 21) to write to the maxsystemvoltage register. the register address for maxsystemvoltage is 0x15. the 16-bit binary number formed by d15-d0 represents the max system voltage set point in mv. however, the resolution of the isl9519c is 16mv because the d0-d3 bits are ignored, as shown in table 3. the d14 and d15 bits are ignored because they are not needed to span the accepted range. table 3 shows the mapping between the 16-bit number written to the maxsystemvoltage register and max system voltage set point. the maxsystemvoltage register can be read back to verify its contents. smart battery registers the maxsystemvoltage and chargecurrent registers use addresses and the format define d in the smart battery charger specification (level 2) for char gevoltage and char gecurrent. in some systems, the smart battery pack may write commands to these registers in isl9519c. if a smart battery is used with isl9519c, please refer to the smart battery charger specification for details. max accepted max system voltage command commands that produce system vo ltage far higher than normal cell voltage are ignored. the max accepted maxsystemvoltage commands depend on the cell pin. table 4 gives the maximum command that is accepted for 1, 2 and 3 cells. setting minimum system voltage minimum system voltage is set by writing a valid 16-bit number to the minsystemvoltage register. this 16-bit number translates to a 65.535v full-scale voltage. the isl9519c ignores the first 8 lsbs and uses the next 7 bits to set the minsystemvoltage dac. the minimum system voltage range of the isl9519c is 0v to 19.2v. numbers requesting minimum system voltage greater than 19.2v result in a minimum system voltage of 19.2v. upon initial power-up of the vsmb supply, the minsystemvoltage register is reset to the por value in table 3. use the write-word protocol (figure 21) to write to the minsystemvoltage register. the register address for minsyste mvoltage is 0x3e. the 16-bit binary number formed by d15-d0 represents the min system voltage set point in mv. however, the resolution of the isl9519c is 256mv because the d0-d7 bits are ignored, as shown in table 5. the d15 bit is also ignored be cause it is not needed to span the 0v to 19.2v range. table 5 shows the mapping between the 16-bit number written to the mi nsystemvoltage register and the min system voltage set point. th e minsystemvoltage register can be read back to verify its contents. table 3. maxsystemvoltage (register 0x15) bit bit name description 0 to 3 not used. 4 maxsystemvoltage, maxsvdac 0 0 = adds 0mv of charger voltage, 1 = adds 16mv of charger voltage. 1024mv minimum 5 maxsystemvoltage, maxsvdac 1 0 = adds 0mv of charger voltage, 1 = adds 32mv of charger voltage. 1024mv minimum 6 maxsystemvoltage, maxsvdac 2 0 = adds 0mv of charger voltage, 1 = adds 64mv of charger voltage. 1024mv minimum 7 maxsystemvoltage, maxsvdac 3 0 = adds 0mv of charger voltage, 1 = adds 128mv of charger voltage. 1024mv minimum 8 maxsystemvoltage, maxsvdac 4 0 = adds 0mv of charger vo ltage, 1 = adds 256mv of charger voltage. 1024mv minimum 9 maxsystemvoltage, maxsvdac 5 0 = adds 0mv of charger voltage, 1 = adds 512mv of charger voltage. 1024mv minimum 10 maxsystemvoltage, maxsvdac 6 0 = adds 0ma of charger voltage. 1 = adds 1024mv of charger voltage. 11 maxsystemvoltage, maxsvdac 7 0 = adds 0mv of charger voltage. 1 = adds 2048mv of charger voltage. 12 maxsystemvoltage, maxsvdac 8 0 = adds 0mv of charger voltage. 1 = adds 4096mv of charger voltage. 13 maxsystemvoltage, maxsvdac 9 0 = adds 0mv of charger voltage. 1 = adds 8192mv of charger voltage. 14 not used. normally a 16384mv weight 15 not used. normally a 32768mv weight. table 4. max accepted max system voltage command # of cells max accepted command min ignored command 1 (cell = floating) 0x17f0 (6.128v) 0x1800 2 (cell = gnd) 0x27f0 (10.224v) 0x2800 3 (cell = vsmb) 0x3ff0 (16.368v) 0x4000
isl9519c 18 fn7823.0 june 30, 2011 bgate and 1 cell operation when operating with a 1 cell battery, the bgate fet must have a low threshold voltage (v th ) and low r dson with v gs = 2.5v. the v gs at 256ma must be less than the programmed minsystemvoltage -1.2v. for example, if the minimum system voltage is 3.072v, the bgate fets v gs at id = 256ma must be less than 1.872v (i.e., 3.072v-1.2v). if the bgate fets v th is over 2v, and the minimum system voltage is 3.072v, bgate will pull below 1.2v in the linear mode, and may not switch isl9519c to trickle charge current. setting charge current the isl9519c has a 16-bit charge current register that sets the battery charging current. the isl9519c controls the charge current by controlling the csop-cson voltage. the register?s lsb translates to 10v at cson-csop. with a 10m ? charge current r sense resistor (rs2 in the ?typical application circuit? on page 6), the lsb translates to 1ma charge current. the isl9519c ignores the first 7 lsbs and uses the next 6-bits to control the current dac. the charge-current range of the isl9519c is 0a to 8.064a (using a 10m ? current-sense resistor). all numbers requesting charge current above 8.064a result in a current setting of 8.064a. all numbers requesting charge current between 0ma to 128ma result in a current setting of 0ma. after initial power-up of vsmb, the chargecurrent register is reset to 0x0000, bgate is high (bgate fet is off) and charging is disabled. to charge the battery, write a valid, non-zero number to the chargecurrent register. the chargecurrent register uses the write-word protocol (figure 21). the register code for chargecurrent is 0x14 (0b00010100). table 6 shows the mapping between the 16-bit chargecurrent number and the charge current set point. the chargecurrent register can be read back to verify its contents. table 5. min system voltage (register 0x3e) bit bit name description 0 to 7 not used. 8 minsystemvoltage, minsvdac 0 0 = adds 0mv of charger voltage, 1024mv minimum 1 = adds 256mv of charger voltage. 9 minsystemvoltage, minsvdac 1 0 = adds 0mv of charger voltage, 1024mv minimum 1 = adds 512mv of charger voltage. 10 minsystemvoltage, minsvdac 2 0 = adds 0ma of charger voltage. 1 = adds 1024mv of charger voltage. 11 minsystemvoltage, minsvdac 3 0 = adds 0mv of charger voltage. 1 = adds 2048mv of charger voltage. 12 minsystemvoltage, minsvdac 4 0 = adds 0mv of charger voltage. 1 = adds 4096mv of charger voltage. 13 minsystemvoltage, minsvdac 5 0 = adds 0mv of charger voltage. 1 = adds 8192mv of charger voltage. 14 minsystemvoltage, minsvdac 6 not used. 15 - not used. table 6. chargecurrent (register 0x14) (10m sense resistor, rs2) bit bit name description 0 to 6 not used. 7 charge current, ccdac 0 0 = adds 0ma of charger curren t. 1 = adds 128ma of charger current. (rs2 = 10m ? ) 8 charge current, ccdac 1 0 = adds 0ma of charger curr ent. 1 = adds 256ma of charger current. (rs2 = 10m ? ) 9 charge current, ccdac 2 0 = adds 0ma of charger curren t. 1 = adds 512ma of charger current. (rs2 = 10m ? ) 10 charge current, ccdac 3 0 = adds 0ma of charger curr ent. 1 = adds 1024ma of charger current. (rs2 = 10m ? ) 11 charge current, ccdac 4 0 = adds 0ma of charger curr ent. 1 = adds 2048ma of charger current. (rs2 = 10m ? ) 12 charge current, ccdac 5 0 = adds 0ma of charger curr ent. 1 = adds 4096ma of charger current, (rs2 = 10m ? ) 8064ma maximum 13 to 15 not used.
isl9519c 19 fn7823.0 june 30, 2011 setting input current limit when the input current exceeds th e set input current limit, the isl9519c decreases the charge current to provide priority to system load current. as the system load rises, the available charge current drops linearly to zero. higher system loads can be drawn from the battery. if the battery is not present, the system voltage is reduced to supply more system current at the same input current. the total input current can increase to the limit of the ac-adapter. the internal amplifier compares the differential voltage between csip and csin to a scaled vo ltage set by the inputcurrent register. the total input current is a function of battery charge current, system load current, v out , v in and efficiency. the total input current can be estimated by equation 2: where is the efficiency of the dc/dc converter (typically 90% to 95%). the isl9519c has a 16-bit inputcur rent register th at translates to a 1ma lsb and a 65.53a full scale current using a 20m ? current-sense resistor (rs1 in figure 4). equivalently, the 16-bit input current number sets the voltage across csip and csin inputs in 20v per lsb increments. to set the input current limit, use the smbus to write a 16-bit inputcurrent register using the data format listed in table 7. the inputcurrent register uses the write-word protocol (see figure 21). the register code for inputcurrent is 0x3f (0b00111111). the inputcurrent register can be read back to verify its contents. the isl9519c ignores the first 7 ls bs and uses the next 6-bits to control the input current dac. the input current range of the isl9519c is from 128ma to 8.064a. all 16-bit numbers requesting input current above 8.0 64a result in an input-current setting of 8.064a. the default inpu t current limit setting at power on of vsmb is the por value in table 2 on page 16. i input i system i battery + () v system v input () ? = (eq. 2) table 7. input current (register 0x3f) (20m sense resistor, rs1) bit bit name description 0 to 6 not used. 7 input current, acdac 0 0 = adds 0ma of input cu rrent. 1 = adds 128ma of input current. (rs1 = 20m ? ) 8 input current, acdac 1 0 = adds 0ma of input cu rrent. 1 = adds 256ma of input current. (rs1 = 20m ? ) 9 input current, acdac 2 0 = adds 0ma of input cu rrent. 1 = adds 512ma of input current. (rs1 = 20m ? ) 10 input current, acdac 3 0 = adds 0ma of input curre nt. 1 = adds 1024ma of input current. (rs1 = 20m ? ) 11 input current, acdac 4 0 = adds 0ma of input cu rrent. 1 = adds 2048ma of input current. (rs1 = 20m ? ) 12 input current, acdac 5 0 = adds 0ma of input cu rrent. 1 = adds 4096ma of input current. (rs1 = 20m ? ) 8064ma maximum 13 to 15 not used. table 8. control register (register 0x3d) bit bit name description 0s gate on s gate on = 1 forces isl9519c to turn the sgate fet on. s gate on = 0 allows isl9519c to turn sgate off if adapter current in below a min threshold 1 80khz when isl9519c is in variable frequency mode, 80khz = 1 sets min frequency to 80khz. 80khz = 0 sets min frequency to 140khz 2 isolate adapter isolate adapter = 1 disconnects the adapter from the charger by making the agate pin hi z. default 0 3 variablefreq 0: forces fixed frequency operation of the buck regulator; 1: allows variable frequency 4 lowpower lowpower = 1 removes power from the batt ery discharge monitor circuits to reduce power consumption. default 0 5 selvfbit 0: listens to vfsw pin; 1: listens to variablefreqbit 6 ac_ok read only. the chip indi cates the state. default 0. 7 trickle read only. the chip in dicates the state. default 0. 8 to 15 not used.
isl9519c 20 fn7823.0 june 30, 2011 control register each bit in the control register has a different function. table 8 describes the actions of each bit. the register can be read or written. bits 6 and 7 are controlled internally and are read only. writing to bits 7 and 6 does not change their value or the function of isl9519c. the register returns to its default values on power-up of vsmb (see table 2 on page 16). charger timeout the isl9519c includes a timer to insure the smbus master is active and to prevent over charging the battery. if the adapter is present and if isl9519c does not receive a write to the maxsystemvoltage or chargecurrent register within 175s, isl9519c will terminate charging by turning the bgate fet off. if a time-out occurs, either the maxsystemvoltage or the chargecurrent register must be written to in order to re-enable charging. isl9519c will continue to regulate the system voltage even if an smbus time-out occurs. if the adapter is not present, isl9519c turns the bgate fet on to supply system voltage from the battery. isl9519c data byte order each register in isl9519c contains 16-bits or two, 8-bit bytes. all data sent on the smbus is in 8-bit bytes and 2 bytes must be written or read from each register in isl9519c. the order in which these bytes are transmitted appears reversed from the way they are normally written. the lo byte is sent first and the hi byte is sent second. for example, when writing 0x41a0, 0xa0 is written first, and 0x41 is sent second. (see figure 21.) writing to the internal registers in order to set the chargecurrent, inputcurrent, maxsystemvoltage, minsystemvoltage or the control registers, valid 16-bit numbers must be written to isl9519c?s internal registers via the smbus. to write to a register in the isl9519c, the master sends a control byte with the r/w bit set to 0, indicating a write. if it receives an acknowledge from the isl9519c it sends a register address byte setting the register to be written (i.e., 0x14 for the chargecurrent register). the isl9519c will respond with an acknowledge. the master then sends the lower data byte to be written into the desired register. the isl9519c will respond with an acknowledge. the master then sends the higher data byte to be written into the desired register. the isl9519c will respond with an acknowledge. the master then issues a stop condition, indicating to the isl9519c that the current transaction is complete. once th is transaction completes, the isl9519c will begin operating at the new current or voltage (see figure 21). the isl9519c does not support writing more than one register per transaction. reading from the internal registers the isl9519c has the ability to read from 7 internal registers. prior to reading from an internal register, the master must first select the desired register by writing to it and sending the registers address byte. this process begins by the master sending a control byte with the r/w bit set to 0, indicating a write. once it receives an acknowledge from the isl9519c, it sends a register address byte representing the internal register it wants to read. the isl9519c will respond with an acknowledge. the master must then respond with a stop conditio n. after the stop condition the master follows with a new star t condition, then sends a new control byte with the isl9519c slave address and the r/w bit set to 1, indicating a read. the isl9519c will acknowledge then send the lower byte stored in that register. after receiving the byte, the master acknowledges by holding sda low during the 9th clock pulse. the isl9519c then sends the higher byte stored in the register. after the second byte neither device holds sda low (no acknowledge). the master will then produce a stop condition to end the read transaction (see figure 21). the isl9519c does not support reading more than 1 register per transaction. application information the following battery charger design refers to the ?typical application circuit? on page 6 in figure 4. this section describes how to select the external comp onents including the inductor, input and output capacitors, switching mosfets and current sensing resistors. inductor selection the inductor selection has tr ade-offs between cost, size, crossover frequency and efficiency. for example, the lower the inductance, the smaller the size, bu t ripple current is higher. this also results in higher ac losses in the magnetic core and the windings, which decreases the system efficiency. higher inductance results in lower ripple current and smaller output filter capacitors, but it has hi gher dcr (dc resistance of the inductor) loss, lower saturation current and has slower transient response. so, the practical inductor design is based on the inductor ripple current being 15% to 20% of the maximum operating dc current at maximum input voltage. maximum ripple is at 50% duty cycle or v bat =v in,max /2. the required inductance for 15% ripple current can be calculated from equation 3: where v in,max is the maximum input voltage, f sw is the switching frequency and i out,max is the max dc current required by the system. for v in,max = 20v, v bat = 12.6v, i bat,max = 4.5a, and f s = 400khz, the calculated induct ance is 9.3h. choosing the closest standard value gives l = 10h. ferrite cores are often the best choice since they are optimized at 400khz to 600khz operation with low core loss. the core must be large enough not to saturate at the peak inductor current i peak in equation 4: l v in max , 4f sw 0.3 i ? out max , ?? ------------------------------------------------------------- - = (eq. 3)
isl9519c 21 fn7823.0 june 30, 2011 inductor saturation can lead to cascade failures due to very high currents. conservative design limits the peak current in the inductor to less than 90% of the rated saturation current. crossover frequency is heavily dependent on the inductor value. f co should be less than 20% of the switching frequency and a conservative design has f co less than 10% of the switching frequency. the highest f co is in voltage control mode with the battery removed and may be calculated (approximately) from equation 5: output capacitor selection in narrow vdc systems, one or more capacitors are connected at the charger output (cson) and a large number of capacitors are connected to the system voltage output. most of the system voltage capacitors are placed near the inputs to the system and core regulators. some capacitance (on the order of 20f to 100f) with low esr should be placed near the inductor and fets to provide a path for switching currents that is short and has a small area. a combination of 0.1f, 10f ceramic capacitors and organic polymer capacitors are a good choice for capacitors near the isl9519c and the inputs to the other system regulators. organic polymer capacitors have high capacitance with small size and have a significant equivalent seri es resistance (esr). although esr adds to ripple voltage, it al so creates a high frequency zero that helps the closed loop operation of the buck regulator. snubber design isl9519c's buck regulator operates in discontinuous current mode (dcm) when the load current is less than half the peak-to-peak current in the inductor. after the low-side fe t turns off, the phase voltage rings due to the high impedance with both fets off. this can be seen in figure 24. adding a snubber (resistor in series with a capacitor) from the phase node to ground can grea tly reduce the ringing. in some situations a snubber can improve output ripple and regulation. the snubber capacitor should be approximately twice the parasitic capacitance on the phase node. this can be estimated by operating at very low load current (100ma) and measuring the ringing frequency. other capacitor values can be used but smaller values will allow some ringing and larger values will increase the power dissipated in the snubber resistor. c snub and r snub can be calculated from equations 6 and 7: input capacitor selection the input capacitor absorbs the ripple current from the synchronous buck converter, which is given by using equation 8: this rms ripple current must be smaller than the rated rms current in the capacitor datasheet. non-tantalum chemistries (ceramic, aluminum, or oscon) are preferred due to their resistance to power-up surge cu rrents when the ac-adapter is plugged into the battery charger. for notebook battery charger applications, it is recommended that ceramic capacitors or polymer capacitors from sanyo be used due to their small size and reasonable cost. loop compensation design isl9519c has four closed loop control modes. one controls the output voltage when the battery is fully charged or absent. a second controls the current into the battery when charging, the third limits current drawn from the adapter and the fourth controls the minimum system voltage. the charge current and input current control loops are compensated by a single capacitor on the icomp pin. the voltage control loops are compensated by a network shown in figure 24. descriptions of these control loops and guidelin es for selecting compensation components will be given in the following sections. which loop controls the switching regulator is determined by the minimum current buffer and the minimum voltage buffer (imin and vmin in figure 3). these four loops will be described separately. transconductance amplif iers gm1, gm2, gm3 and gm4 the isl9519c uses several tran sconductance amplifiers (also known as gm amps). most commer cially availabl e op amps are voltage controlled voltage sources with gain expressed as a=v out /v in . gm amps are voltage contro lled current sources with gain expressed as gm = i out /v in . gm will appear in some of the equations for poles and zeros in the compensation. pwm gain f m the pulse width modulator in the isl9519c converts voltage at vcomp (or icomp) to a duty cycle by comparing vcomp to a triangle wave (duty = vcomp/v p-p ramp ). the low-pass filter formed by l and c o convert the duty cycle to a dc output voltage (v out =v dcin *duty). in isl9519c, the triangle wave amplitude is proportional to v dcin . making the ramp am plitude proportional to dcin makes the gain from vcomp to the phase output a constant 11 and is independent of dcin. i peak i out max , 1 2 -- - + i ripple ? = (eq. 4) f co 511r sense ?? 2 l ? --------------------------------------- - = (eq. 5) c snub 2 2 f ring () 2 l ? ----------------------------------- - = (eq. 6) r snub 2l ? c snub ----------------- = (eq. 7) i rms i bat v out v in v out ? () ? v in ------------------------------------------------------ ? = (eq. 8)
isl9519c 22 fn7823.0 june 30, 2011 output lc filter transfer functions the gain from the phase node to the system output and battery depend entirely on external components. transfer function a lc (s) is shown in equations 9 and 10: the load resistance r o is a combination of mosfet r ds(on) , inductor dcr and the internal resistance of the battery (normally between 50m ? and 200m ? ) in parallel with the system. the system load may be modeled as a current sink in parallel with a resistance. for ac analysis of the voltage control loop, this may be treated as a very high resistan ce or an open circuit. the worst case for voltage mode control is when the battery is absent. this results in the highest q of the lc filter and the lowest phase margin. when the battery is present, the q is very low (typically 0.1). with very low q the double pole from the lc filter split into two separate poles, one at frequency below dp and one at a frequency above dp . max system voltage control loop the max system voltage error ampl ifier controls the output when the input current is below the limit and the battery is charged to the value in the maxsystemvoltage register. under these conditions, vcomp controls the charger?s output because the 2 current error amplifiers (gm1 and gm3) output their maximum current and charge the capacitor on icomp to its maximum voltage (clamped to 0.3v above vcomp). with icomp higher than vcomp, the minimum voltag e buffer output equals the voltage on vcomp. the max system voltage control loop is shown in figure 24. the compensation network consists of the max system voltage error amplifier gm2 and the compensation network r 1 , c 1 , r 2 and c 2 . equations 11 through 16 relate to the compensation network?s poles, zeros and gain to the components in figure 24. figure 25 shows an asymptotic bode plot of the dc/dc converter?s gain vs frequency. it is strongly recommended that f z1 is approximately 1/4*f dp, and f z2 is approximately 1/2*f dp. compensation break frequency equations figure 22. for small signal ac analysis, the pwm and power stage can be modeled as a simple gain of 11 drivers ramp gen v ramp = v in /11 v in - + 11 vcomp vcomp l l r esr c o c o r esr a lc 1 s esr ------------- - ? ?? ?? s 2 dp ---------- - s dp q ? () ------------------------ 1 ++ ?? ?? ?? --------------------------------------------------------- - = (eq. 9) esr 1 r esr c o ? () ----------------------------- = dp 1 lc o ? () ---------------------- - = qr o l c o ----- - ? = (eq. 10) -70 -60 -50 -40 -30 -20 -10 0 10 100 200 500 1k 2k 5k 10k 20k 50k 100k 200k 500k -140 -120 -100 -80 -60 -40 -20 figure 23. frequency response of the lc output filter phase () gain (db) frequency (hz) r battery = 100m ? r battery = 50m ? no battery f z1 1 2 c 1 r 1 r 3 + () ?? () ---------------------------------------------------- - = (eq. 11) f z2 1 2 c 2 r 2 1 gm2 ------------ ? ?? ?? ?? ?? ?? ?? ?? ------------------------------------------------------------ - = (eq. 12) 1 gm2 ------------ 4000 = (eq. 13) f dp 1 2 lc o ? () ------------------------------ = (eq. 14) f p1 1 2 r 1 c 1 ?? () ---------------------------------- - = (eq. 15) f esr 1 2 c o r esr ?? () ----------------------------------------- = (eq. 16)
isl9519c 23 fn7823.0 june 30, 2011 . charge current control loop when the battery voltage is less than the programmed max system voltage, the max system voltage error amplifier goes to it?s maximum output (limited to 0.3v above icomp) and the icomp voltage controls the loop through the minimum voltage buffer. figure 26 shows the charge current control loop. the compensation capacitor (c icomp ) gives the error amplifier (gm1) a pole at a very low freq uency (<<1hz) and a zero at f z1 . f z1 is created by the 0.25*ca2 output added to icomp. the loop response has another zero due to the output capacitor?s esr. a filter should be added between r s2 and csop and cson to reduce switching noise. the filter roll off frequency should be between the crossover frequency and the switching frequency (~100khz). r f2 should be small (<2 ? ) to minimize offsets due to leakage current into csop. figure 24. max system voltage loop compensator ramp gen vramp = vin /11 vin l r s2 r esr co r bat r 1 r 2 500k 100k c 2 c 1 vcomp - + for small signal ac anal ysis, voltage sources are short circuits and current sources are open circuits. r 1 r 2 500k 100k c 2 c 1 system r s2 r bat fb cson phase vcomp fb cson phase resr c o 11 drivers + - gm2 + - gm2 maxsvdac -40 -30 -20 -10 0 10 20 30 40 50 60 0.01 0.1 1 10 100 1k frequency (hz) gain (db) loop modulator compensator f dp f p1 f zesr f z1 f z2 figure 25. asymptotic bode plot of the max system voltage control loop gain figure 26. charge current limit loop r s2 r bat icomp cson phase r esr c o 11 + - ca2 20 csop s + - 0.25 + - gm1 l c f2 r f2 c icomp ccdac f dp 1 2 lc o ? () ------------------------------ = (eq. 17) f zesr 1 2 c o r esr ?? () ----------------------------------------- = (eq. 18) f z1 4gm1 ? 2 c icomp ? () ------------------------------------ - = (eq. 19) gm1 50 av ? = (eq. 20) f filter 1 2 c f2 r f2 ?? () ---------------------------------------- - = (eq. 21)
isl9519c 24 fn7823.0 june 30, 2011 c icomp should be chosen using equation 22 to set f z1 =f dp /10. the crossover frequency wi ll be approximately 2.5*f dp . the phase margin will be betwee n +10 and +40 depending on f zesr . adapter current limit control loop if the combined battery charge current and system load current results in adapter current that equals the programmed adapter current limit, isl9519c will reduce the current to the battery and/or reduce the output voltage to hold the adapter current at the limit. above the adapter curre nt limit, the minimum current buffer equals the output of gm 3 and icomp controls the charger output. a filter should be added between r s1 and csip and csin to reduce switching noise. the filter roll off frequency should be between the crossover frequency and the switching frequency (~100khz). the loop response equations, bo de plots and the selection of c icomp are the same as the charge cu rrent control loop with loop gain reduced by the duty cycle. in other words, if the duty cycle d = 50%, the loop gain will be 6db lower than the loop gain in figure 27. this gives lower crossover frequency and higher phase margin in this mode. the current control loops can have the same gain if the input current sense resistor is larger than the charge current sense resistor by the same ratio that input voltage is larger than output voltage. min system voltage control loop the min system voltage control loop is only active when a battery is connected that is discharged to a voltage below the voltage in the minsystemvoltage register. wh en it is active, the isl9519c reduces the charge current to 256ma and controls the bgate fet in the linear range to hold the min system voltage on the system output. the reduced charge current and active bgate control are referred to in this document as ?trickle charge mode?. when the battery voltage is higher than min system voltage, bgate goes approximately 7v below the system voltage (at cson) to fully enhance the bgate fet. in 1-cell systems bgate will pull to ground. a bgate fet should be selected that is fully enhanced with minsystemvoltage between gate and source. when the battery voltage is less than the min system voltage, the min system voltage loop controls the voltage on bgate to hold the system voltage at the programmed min system voltage. the voltage difference between the min system voltage and the battery voltage drops across the bgate fet. guidelines for layout and component placement signal ground (agnd) and power ground (pgnd) connection the isl9519c has 2 ground co nnections; agnd and pgnd. agnd should connect to all low power and sensitive circuits, such as compensation and current sensing. pgnd should be connected to all high power circuits, such as the switching fets and bypass caps. agnd should be connected to pgnd at a single point at the isl9519c. pgnd should connect to the main system ground plane at a single po int very near the isl9519c. pgnd is connected internally to the source of the lower fet and the fet driver circuits. it should be connected externally to the bypass capacitors on the output power (vsystem caps and vbattery caps) and input power (vddp cap and the caps at vin. the pgnd pin should be connected to the main system ground plane at one point very close to the isl9519c. -60 -40 -20 0 20 40 60 0.01 0.1 1 10 100 1k frequency (hz) gain (db) loop modulator compensator f dp f zesr f z1 f filter figure 27. charge current loop bode plots c icomp 4gm1 ? 2 f dp 10 ? ? -------------------------------- - = (eq. 22) figure 28. adapter current limit loop l c icomp r bat icomp phase r esr c o 11 s + - 0.25 + - gm3 r s1 dcin csin + - 20 csip c f1 r f1 r s2 cson + - 20 csop c f2 r f2 acdac
isl9519c 25 fn7823.0 june 30, 2011 agnd is internally connected to the ic substrate and all of the small signal circuits in the ic. all connections to ground from the following list of pins should connect to an area of copper that is separate from the main ground plane and pgnd (dcin, adet, icomp, vcomp, cell, amon, vsmb, vdd, csin, csip). please refer to figure 4 for details of the connections to agnd and pgnd. this separate area of ground should be connected to both the agnd and pgnd pins at (under) the isl9519c. the thermal pads on the ic have the lowest thermal resistance path to the conduct heat away from the ic and fets. pad 51 (agnd) should be connected to other agnd pins. pad 52 (phase) is the thermal pad for the lower fet. pad 53 is the thermal pad for the upper fet. pads 52 and 51 should be connected with several vias to areas of copper to minimize the thermal resistance from the ic to the ambient air. see figure 29 for an example of the pattern of vias in the thermal pad. vin (input power) capacitors it is recommended that ceramic capacitors be used closely connected to vin and pgnd. this capacitor reduces the noise and the power loss of the mosfet. the capacitors should be on the same layer as isl9519c to avoid vias between isl9519c and bypass caps. vddp at least one high quality ceramic decoupling cap should be connected from vddp to pgnd. the decoupling cap should be put close to the ic. vddp is the power input to the gate drivers. the decoupling cap should be placed close to isl9519c on the same layer. ugate this pin connects the upper fet gate to the driver. a 4700pf cap should be connected to reduce dv/dt. phase this trace should be short, and positioned away from other weak signal traces. this node has a ve ry high di/dt and dv/dt with a voltage swing from the input voltage to ground. it is the return path for upper fet gate drive currents. copper size for the phase node the capacitance of phase should be kept very low to minimize ringing. it would be best to lim it the size of the phase node copper in strict accordance with the current and thermal management of the application. figure 29. agnd and pgnd agnd pgnd small signal circuits system ground plane ugate vddp phase analog ground area gate drivers csip icomp vdd csin isl9519c system loads input power pgnd vin
isl9519c 26 fn7823.0 june 30, 2011 boot this pin?s di/dt is as high as the ugate; therefore, this trace should be as short as possible. vdd at least one high quality ceramic decoupling cap should be connected from vdd to agnd. th e decoupling cap should be placed close to the ic. vdd is the output of an internal regulator and the supply for most of the smal l signal circuits in the ic. the vdd decoupling cap should be placed close to the isl9519c and on the same layer. the ground end of the vdd decoupling cap should connect through a via to the separate agnd area on the layer adjacent to the isl9519c. csop, cson, csip and csin accurate charge current and adap ter current sensing is critical for good performance. the curren t sense resistor connects to the cson and the csop pins through a low pass filter with the filter capacitor very near the ic (see figure 4). traces from the sense resistor should start at the pads of the sense resistor and should be routed close together through the low pass filter and to the csop and cson pins (see figure 30). the cson pin is also used as the system voltage feedback. the traces should be routed away from the high dv/dt and di/dt pins like phase, boot pins. in general, the current sense resi stor should be close to the ic. these guidelines should also be followed for the adapter current sense resistor and csip and cs in. other layout arrangements should be adjusted accordingly. figure 30. current sense resistor layout high current trace high current trace kelvin connection traces to the low pass filter and csop and cson sense resistor
isl9519c 27 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7823.0 june 30, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl9519c to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change june 30, 2011 fn7823.0 initial release
isl9519c 28 fn7823.0 june 30, 2011 package outline drawing l50.5x7b 50 lead quad flat no-lead plastic package rev 0, 12/10 2x 3.20 3.50 36x 0.40 42 50 1 pin #1 4 0.10 2x 6.00 2x 0.60 50x 0.20 0.05 b a m c 2x 1.00 26 41 6x 0.15 0.296 1.40 1.40 25 17 0.5885 6x 0.1950 16 1.875 3.10 46x 0.40 0.35 2.00 1.725 1.275 2.67 0.48 bottom view detail "x" side view typical recommended land pattern top view 0.10 seating plane 0.00 min. c 0 . 2 ref 5 0.08 c c c see detail "x" max. 1.0 0.10 2x 7.00 b index area 5.00 pin 1 a (46x 0.40) package (0.7885) (1.40) (6x 0.395) (5.40) (4.20) (1.40) (0.496) (1.275) (0.35) (2x 6.0) (1.875) pin one (2x 7.4) (50x 0.20 0.05) (2.02) (2.87) (3.10) (36x 0.60) (2x 3.20) (3.50) (2x 6.0) (1.725) 0.05 max. 0.48 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.10 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.015mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: angular 2.50 identification outline 6

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